Conventionally, a clamp level reference signal which is multiplexed with an image signal is used for detection of an amount of noise in addition to DC level restoration of the original image signal. A method of restoring a DC level is disclosed in the Japanese Unexamined Patent Publication JP-A-58-124373, for example. A method of performing the detection of the noise amount and control of a reproduction apparatus, by using the clamp level reference signal multiplexed with the image signal, is disclosed in the Japanese Unexamined Patent Publication JP-A-62-172879, for example. FIG. 1 shows an arrangement of a conventional image receiver control apparatus, in which the restoration of the DC level, the detection of the noise amount and automatic gain control are performed by using the above methods.
In FIG. 1, numeral 1 indicates an input signal, numeral 2 an analog clamper, numeral 3 an A/D converter and numeral 4 a digital output signal. The input signal 1 is clamped on a predetermined value by the analog clamper 2 and then the clamped signal is converted into, for example, an 8-bit digital signal by the A/D converter 3. A digital level comparator 5 determines a difference between a digital value obtained by A/D-converting a portion of the input signal corresponding to a clamp level reference signal and a predetermined digital value, e.g., a value "128". An integrator 6 integrates an output from the digital level comparator 5 and the integrated output is converted into an analog clamp level signal by a D/A converter 7. The analog clamp level signal is connected to the analog clamper 2 to form a feed-back loop, so that control is performed such that an average value of the digital values obtained by A/D-converting predetermined portions of the input signal is "128". Operation speeds of the digital level comparator 5 and the integrator 6 are the same as conversion speed of the A/D converter.
Numerals 8 to 17 indicates a circuit portion for detecting the noise amount. The values obtained by A/D-converting the clamp level reference signal ought to be substantially constant unless the noise is introduced. However, the values are usually different per each sample because of influence of noise on a transmission path. A variance of the sample values from the average value represents energy of the noise. Since generation of noise is a random process, it is necessary to use, as the noise level, a value obtained by processing on many sample values and a low pass filter processing in a time axis direction, i.e., a temporal filter processing to suppress their time variations. A difference between the sample values of the A/D-converted signal 4, one of which is delayed by one period of the same operation clock signal (to a terminal 19) as that of the A/D converter, is calculated by a flip-flop 8 and a subtracter 9. Then, the difference is sampled in a flip-flop 10 in response to the clock signal (b) supplied from a terminal 20. Next, a difference between the sampled values, one of which is delayed by one period of the clock signal (a) from a terminal 20, is determined by a flip-flop 11 and a subtracter 12. The timing when the clock signal (b) rises is during a period of the clamp level reference signal and indicates a timing of a signal used for noise detection. An absolute value of the difference is determined by a circuit indicated by numeral 13 and a signal corresponding to a noise level is obtained from the absolute value by a low pass filter in a time axis direction, i.e., a temporal filter 14. The temporal filter 14 is arranged as shown in FIG. 2 to suppress time variations of the input signal.
In FIG. 2, numeral 21 indicates a subtracter, numeral 22 an amplifier of gain K1, numeral 23 an adder, numeral 24 a delay circuit, and numeral 25 an amplifier of gain K2. A circuit portion constituted by the amplifier 22, the adder 23 and the delay circuit 24 is a digital integrator 26. More particularly, a value obtained by multiplying an input to the integrator 26 by K1 is added to a previous value, and hence, when a constant input value is given, an output of the integrating circuit varies with an inclination proportional to the input value. The subtracter 21 is provided before the integrating circuit, and a signal obtained by multiplying the output from the integrator by K2 by the amplifier 25 is supplied to the subtracter 21 to form a feed-back loop, as shown in FIG. 2. With such an arrangement, when an adequate positive input (f) is given, the output from the integrator 26 increases gradually. However, the greater the output from the delay circuit 24 becomes, the greater the fed-back value becomes. As a result, the output of the subtracter 21 obtained by subtracting the output of the amplifier 25 from the input (f) becomes so small that the output from the integrator 26 varies slowly. Ultimately, the output from the integrator 26 is made stable to be a constant value proportion t the input value.
Therefore, the circuitry arranged as shown in FIG. 2 functions as a so-called temporal filter for suppressing variations in the time direction. A threshold circuit 15 quantizes the detected noise amount (c) into, for example, four levels to switch a degree of noise reduction into four levels.
Numerals 16 to 18 indicates a system for automatic gain control. A deviation of an amplitude reference signal, which is included in a digital signal into which the input analog signal from the terminal 1 is converted by the A/D converter 3, from a predetermined value is detected by a digital gain detector 16. Closed loop DC gain is made so great by the integrating circuit 17, as well as influence of noise is eliminated, that an offset error does not occur. An output from the integrator 17 is converted into an analog signal by a D/A converter 18 and the converted analog signal is supplied to the A/D converter 3 as an A/D reference voltage (e) to form a feed-back loop for control of the gain of the A/D converter 3 such that a signal obtained by A/D-converting the amplitude reference signal of the input signal represents a predetermined digital value.
However, in the image receiver control apparatus of such a system, a system for calculating the clamp level, a system for detecting the noise level and a system constituted by many circuits of the apparatus for the automatic gain control are separately provided. Therefore, there is a problem in that the apparatus needs large scale hardware. In addition, many circuits of the apparatus such as the digital level comparator 6, the integrators 6, 17, and 26 and the like need to be able to operate with the same operation clock signal (a) having a relatively high frequency as that for the A/D converter. Therefore, there is a problem in that the conventional apparatus has the disadvantage in power consumption. Further, since the detected noise level is only quantized into about four levels for control of noise reduction, the noise reduction level changes frequently in a step manner because of slight fluctuation of the remaining noise level when the noise level (c) is accidentally close to one of a plurality of threshold values of the threshold circuit 15. More particularly, although the noise level included in the input signal supplied from the terminal 1 does not change substantially, the noise reduction level occasionally changes. This means that a S/N ratio of display on a screen changes during receiving the image such as a still image. Therefore, there is a problem in that the conventional apparatus has a disadvantage of remarkable quality degradation in the received image from a viewpoint of visual psychology. Moreover, operations of the clamp level processing circuit and the automatic gain control circuit are not connected with each other. Therefore, there is a problem in that the clamp level processing operation and the automatic gain control operation occasionally interfere with each other, so that there is a possibility that the operations become astable.
A case wherein the clamp level processing operation and the automatic gain control operation interfere with each other will be described below. As means for gain control, there is a method of controlling a conversion factor or ratio between the input analog signal and the output digital value by changing a reference voltage of the A/D converter. Many of A/D converters generally have such reference voltage input terminals. The above scheme is effective since gain control by means of such a method is simple in configuration and does not need a special gain control amplifier or the like. Generally, in the inside of the A/D converter, there are a reference voltage for determining an input analog level which provides a maximum of the output digital value and a reference voltage for determining the input analog level which provides a minimum of the output digital value, and a difference between these two voltages is reversely proportional to A/D conversion gain. However, there is an A/D converter in which only one of the these reference voltages is provided to the outside of the converter or can hardly be changed in order for securing its performance. In such an A/D converter, the conversion gain must be controlled by controlling the other.
FIGS. 3A and 3B show operation examples of the A/D converters in which the conversion gain control is performed by only one of the above reference voltages. In the figure, relations among the reference voltage, the input analog voltage and digital output value are represented. In FIG. 3A, assume that the number of bits of the A/D converter is "8", the reference voltage for determining the input analog level which provides a maximum of the output digital value is V.sub.RT (-1.0 V), and the reference voltage for determining the input analog level which provides a minimum of the output digital value is V.sub.RB (-3.0 V). Also, assume that a reference value of the clamp level for the input analog signal supplied to the terminal 1 is -2.0 V and a corresponding digital signal is "128". In the system operating in such states, assume that a DC restoration level of the input signal supplied to the terminal 1 is not changed and an amplitude of the input signal increases in a step manner. Since the DC restoration level is not changed, the reference value of the clamp level should be remained to be -2.0 V. When the amplitude of the input signal was increased, it is assumed that the reference voltage (e) to the A/D converter 3 is changed from -3.0 V to, for example, -4.0 V by the operation of the automatic gain control system constituted by circuits 16 to 18. As a result, the difference between the voltages V.sub.RT and V.sub.RB becomes so large that the conversion gain of the A/D converter 3 becomes small to compensate for the increase in the amplitude of the input signal. However, when the digital value of a signal obtained by A/D-converting the reference value of the clamp level -2.0 V is a greater value than 128, e.g., 170, an error signal is detected, as well as when the DC restoration level was very much changed from value "128". As a result, there was a possibility that the clamp level control operation became astable or it took a long time until the clamp level would return to its normal state. Since there is no change in the DC restoration level of the input signal, the change of the clamp level ought to be not detected. However, when the A/D converter is used, in which the gain control is performed by only one reference voltage, the disturbance is transferred to the system for performing the clamp level control as if the DC level was simultaneously changed, even though only the gain variation was generated. That is, the conventional apparatus has a drawback that the change in the amplitude of the input signal influences the DC restoration level.